1. Field of the Invention
The present invention relates to output logic macrocells and clock signal allocation circuitry for a programmable logic device (PLD). More particularly, the present invention relates to providing the macrocells and clock signal allocation circuitry so that PLD resources which typically only provided one function can be programmed to provide one of multiple functions.
2. Description of the Related Art
FIG. 1 shows components from a conventional programmable logic device (PLD), including a macrocell 100, typically provided in a macrocell of the PLD. In the portion of the PLD shown, a group of product term (PT) lines PT1-PT4 are provided which may each be selectively connected to a number of array cells (not shown). A sum of product terms output can be provided by connecting the PT lines through an OR gate 102.
To provide polarity control, a PT line, PT4, is typically provided to a polarity determination circuit 110 which provides both the PT4 signal and its inverse as controlled by the polarity selection signal POL and its inverse POL. The output of the polarity determination circuit 110 is fed with the output of OR gate 102 to an exclusive OR gate 120.
The output of the exclusive OR gate 120 is provided to macrocell 100, which typically includes a register 130, pass gates 132 and 134, and a feedback line 136, as well as other components which are not shown in FIG. 1. To provide a registered output, the output of exclusive OR gate 120 is provided through register 130 and pass gate 132 to an output buffer 140. To provide a combinatorial output, the output of the exclusive OR gate 120 is provided through pass gate 134 to output buffer 140. Feedback 136 is provided to couple the signal provided to output buffer 140 back to be selectively connected to individual product term lines PT1-PT4.
Global signals for a reset, preset and a clock are provided to the register 130 of macrocell 100, as well as to other registers of other macrocells in the PLD. Non-global reset, preset and clock signals may also be provided to the registers through a product term line. For instance, using two programmable fuses F2 and F3, as shown in FIG. 1, a reset can be provided to register 130 from product term line PT1.
FIG. 2 shows typical components utilized in register 130. The circuitry includes two latches 200 and 202 connected in series. The Q output of latch 200 is connected to the data input of latch 202 and the clock input of latch 200 is inverted from the clock input of latch 202 to form a D-type flip-flop.
FIG. 3 shows typical circuitry for the latches 200 and 202 of FIG. 2. As shown, the typical latch includes all inverter 300 with its input forming the Q output of the latch and its output forming the Q output of the latch. The latch also includes an inverter 302 with its output connected to the Q output and its input connected to the Q output. A data signal is provided to the Q input of the latch 300,302 through a latch pass gate 304 which receives the clock signal at its gate.
To enable PLD resources to be selectively configured so that register 100 of FIG. 1 may alternatively be used as a latch, additional circuitry (not shown) is typically added to the register circuitry of FIG. 2. The additional circuitry includes an additional pass gate with its gate controlled to provide the Q output of latch 200 directly as the Q output of register 130, bypassing latch 202.
To enable PLD resources to be further selectively configured so that the D-type flip-flop circuitry of register 130 may alternatively be utilized to provide the function of a T-type flip-flop, the PLD needs only to be appropriately programmed. Typical circuitry for a T-type flip-flop is shown in FIG. 4. As shown, the T-type flip-flop includes a D-type flip-flop circuit 130 as shown in FIG. 2. The Q output of the D-type flip-flop 130 is inverted and selectively fed back to the D input of the D-type flip-flop 130. By appropriately programming a PLD so that the feedback line 136 is appropriately connected to product terms connected to the input of register 130 of FIG. 1, such a T-type flip-flop may be created.
A PLD is designed so that its resources may be selectively configured by a user to create the specific circuitry the user desires. Components of the PLD which form only one particular circuit, the particular circuit not being desired by the user, will create a wasted resource, unnecessarily occupying chip space. Such circuitry includes one of the pass gates 132 and 134 for selectively providing the registered and combinatorial modes, since only one mode will be desired. Further, if a latch mode is desired rather than a registered mode, the latch 202 of FIG. 2 will be bypassed and provide a wasted resource. Additionally, if a reset or preset are not desired, additional circuitry provided in a register (not shown) to enable the reset and preset functions will provide a wasted resource.